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final pu b lication# 14395 r e v : d amendment/ 0 issue date : m a y 1994 1 AM79C98 t wisted- p air etherne t t ransceiver (tpex) distinctive char a cteristics n cmos d e vice p ro vides compliant operation and l o w operating current f r om a single + 5 v supp l y n p o wer d o wn mode p ro vides reduced p o wer consumption f or battery-p o wered applications . reset capability all o ws use in remote m a u applications. n pin-selectable twisted-pair receive polarity detection and automatic i n ve r sion of the receive signal . p olarity indication output pin can direct l y drive an le d . n pin-selectable twisted-pair link integrit y t est capability con f orming to the ieee 802.3 standa r d f or 10 b ase- t . link status pin can direct l y drive an le d . n internal twisted-pair transmitter digital predisto r tion ci r cuit reduces medium-induced jitter and ensures compliance with the 10 b ase-t transmit and receive w a ve f orm requirements n pin-selectable sq e t est (hea r tbeat) enable n t ransmit and receive status indications are a v ailable on separate , dedicated pins n a ui loopba c k , jabber cont r ol , and sq e t est functions comp l y with the 10 b ase-t standa r d ieee std 802.3i-1990 general description the am79c9 8 t wisted- p air ethe r ne t t ranscei v er (tpex) is an inte g rated circuit that implements the medium attachment unit (m a u) functions f or the twisted-pair medium, as specied b y the ieee 802.3 standard ( t ype 10base-t) . this d e vice pr o vides the necessa r y elect r ical and functional inter f ace between the ieee 802.3 standard attachment unit inter f ace ( a ui) and the twisted-pair ca b l e . a netwo r k based on the 10base-t standard can use unshielded twisted-pair ca b le s , pr o viding an economi- cal solution to netwo r king b y all o wing the use of e xist- ing telephone wi r ing . the AM79C98 pr o vides a minimal component count and cost-ef f ecti v e solution to the design and implementation of 10base - t standard netwo r k s . tpex pr o vides twisted-pair d r i v er and recei v er circuit s , including on - board transmit digital predisto r tion, re- cei v er squelch, and an a ui po r t with pin-selecta b le sq e t est ena b l e . the d e vice also pr o vides a number of additional f eature s , including pin-selecta b l e t wisted- p air recei v e p ola r ity detection and a utomatic p ola r ity r e v ersal, link status indication, lin k t est disa b le func- tion, and transmit and recei v e statu s . th e t wisted- p air p ola r ity and link status pins can be used to d r i v e leds directl y . the AM79C98 is f ab r icated in cmos technology and requires a single + 5 v suppl y . the d e vice is a v aila b le in 24 - pin skinnydip plastic dual in-line and 28-pin plastic leaded chip car r ier (plcc) pa c kaging.
2 AM79C98 block di a gram 14395 d -1 line receiv er and smar t squelch p olar ity detect and a uto re v ersal rxpol link t est line dr iv er and predistor tion v oltage controlled oscillator collision and loopbac k j ab ber control line receiv er and squelch circuit line dr iv er line dr iv er sqe test t wisted-p air interf ace attachment unit interf ace (a ui) do+ do xmt ci+ ci di+ di rext prdn/rst test rxd rxd+ rcv lnkst txp txp+ txd txd+
amd 3 AM79C98 related amd products part no. description am7996 ieee-802.3/ethernet/cheapernet tap transceiver am79c100 twisted-pair ethernet transceiver plus (tpex+) am79c90 cmos local area network controller for ethernet (c-lance) am79c900 integrated local area communications controller tm (ilacc tm ) am79c940 media access controller for ethernet (mace tm ) am79c960 pcnet-isa single-chip ethernet controller (for isa bus) am79c961 pcnet-isa+ single-chip ethernet controller (with microsoft plug n play support) am79c965 pcnet-32 single-chip ethernet controller (for 386dx, 486 and vl buses) am79c970 pcnet-pci single-chip ethernet controller (for pci bus) am79c974 pcnet-scsi combination ethernet and scsi controller for pci systems AM79C981 integrated multiport repeater plus tm (imr+ tm ) AM79C987 hardware implemented management information base tm (himib tm ) connection diagram top view 14395d-2 dip note: pin 1 is marked for orientation plcc 14395d-3 1 2 24 23 3 4 5 22 21 20 6 7 8 19 18 17 9 10 11 16 15 14 12 13 rcv rxpol rxdC rxd+ sqe^test test txpC txp+ txdC txd+ dv dd av dd ci+ ciC di+ diC xmt lnkst do+ doC prdn/rst rext dv ss av ss 1 3 2 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 2 8 2 7 26 1 5 1 3 1 4 12 1 6 1 7 18 dv ss dv ss xmt lnkst av ss av ss do+ txpC dv dd test sqe^test av dd diC di+ ciC ci+ txd+ rcv doC prdn/rst rxd+ txdC txp+ dv dd rxpol rxdC rext av dd
amd 4 AM79C98 logic symbol 14395d-4 do+ doC di+ diC ci+ ciC sqe test test rext prdn/rst rcv xmt rxpol lnkst txd+ txp+ txdC txpC rxd+ rxdC twisted pair interface AM79C98 dv dd av dd dv ss av ss attachment unit interface (aui)
a m7 9 c 98 5 ordering inform a tion standa r d p r oducts amd standard products are a v aila b le in s e v e r al pa c kages and operating r ange s . the order number ( v alid combination) is f o r med b y a combination of the elements bel o w . v alid combinations v alid combinations list congurations planned to be sup- po r ted in v olume f or this d e vic e . consult the local amd sales of ce to con r m a v ailability of specic v alid combinations and to che c k on n e wly released combination s . AM79C98 device number/description AM79C98 twisted-pair ethernet transceiver (tpex) optional p r ocessing blank = standard processing technology c = cmos electrically erasable p a ck a g e type p = 24- pin plastic dip (pd 3024) j = 28- pin plastic leaded chip carrier (pl 028) speed not applicable v alid combinations AM79C98 p c , jc
6 a m 79 c98 pin description a v dd analog p o wer this pin supplies + 5 v to analog po r tions of th e tpex circuit r y . a v ss analog g r ound this pin is the g round re f erence f or analog po r tions of th e tpex circuit r y . ci+ , ci cont r ol in output aui port differential driver. di+ , di data in output aui port differential driver. do+ , do data out input aui port differential receiver. d v dd digital p o wer this pin supplies + 5 v to digital po r tions of th e tpex circuit r y . d v ss digital g r ound this pin is the g round re f erence f or digital po r tions of tpex circuit r y . lnkst link status open drain , input/output when this pin is tied low, the internal link test receive function is disabled and the transmit and re- ceive functions will remain active irrespective of arriv- ing idle link test pulses and data. tpex continues to generate idle link test pulses irrespective of the status of this pin. as an output, this pin is driven low if the link is identi- fied as functional. however, if the link is determined to be nonfunctional, due to missing idle link test pulses or data packets, then this pin is not driven. in the low output state, the pin is capable of sinking a maximum of 16 ma and can be used to drive an led. this pin is internally pulled high when inactive. prdn/rst p o wer d o wn/reset input , active l o w d r iving this input l o w resets the inte r nal logic o f tpex and places the d e vice in a special p o wer d o wn mod e . in the p o wer d o wn/reset mod e , all output d r i v ers are placed in their inacti v e stat e . rcv receive output this pin is d r i v en high whil e tpex is receiving data on the rxd pins and is t r ans f er r ing the recei v ed signal onto the a ui di pai r . the rcv and xmt pins are simul- taneously d r i v en high du r ing collision. rext external resistor input an e xte r nal precision resistor is connected bet w een this pin and a v dd in order to pr o vide a v oltage re f er- ence f or the inte r nal v oltage-controlled oscillator (vco). rxd+ , rxd receive data input 10base- t port differential receivers. rxpol receive p olarity open drain , input/output the twisted-pair recei v er is capa b le of detecting a re- cei v e signal with r e v ersed pola r ity (wi r ing error) . the rxpol pin is no r mally in the l o w stat e , indicating cor- rect pola r ity of the recei v ed signal . if the recei v er de- tects r e v ersed pola r it y , then this pin is not d r i v en (goes high) and the polarity of subsequent pa c k ets is in- v e r ted . in the l o w output stat e , this pin can sink up to a maximum of 16 ma and is there f ore capa b le of d r iv- ing an le d . this feature can be disabled by strapping this pin low. in this case, the receive polarity correction circuit is disabled and the internal receive signal remains non- inverted, irrespective of the received signal. this pin is inte r nally pulled high when inacti v e . sqe test signal qualit y t est (hea r tbeat) ena b le input , active l o w the sq e t est function is ena b led b y tying this input l o w . this input is inte r nally pulled high when inacti v e .
a m 79 c 98 7 test t est input , active high this pin should be tied high f or no r mal operation . if this pin is d r i v en l o w , tpex will enter loopba c k t est mod e . the type of loopba c k is dete r mined b y the state of th e sqe test pin . if this pin is in the l o w state (station m a u) , tpex t r ans f ers data independently from do to th e txd/txp circuit and from rxd to the di circuit . if the sqe test is in the high state (repeater m a u), then data on the rxd circuit is transmitted ba c k onto th e txd/txp circuit and data on the do circuit is tr ansmitted onto the di pai r . txd+ , txd t ransmit data output 10base- t port differential drivers. txp+ , txp t ransmit predisto r tion output transmit waveform predistortion control. xmt t ransmit output this pin is d r i v en high whil e tpex is receiving data on the a ui do pair and is transmitting data on th e txd/ txp pin s . the xmt and rcv pins are simultaneously d r i v en high du r ing collision.
8 a m79 c 98 functional description the t wisted- p air ethe r ne t t ranscei v er (tpex) com- plies with the requirements specied b y the ieee 802.3 standard f or the attachment unit inter f ace ( a ui) and the standard f or 10base-t medium attachment unit (m a u) . tpex also implements a number of f eatures in addition to the ieee 802.3 standard . an outline of func- tions implemented b y the AM79C98 is gi v en bel o w . attachment unit interface (do+/ , di+/ , ci+/? the a ui elect r ical and functional cha r acte r istics com- ply with those specied b y the ieee 802.3, sections 7 and 14 (d r afted) . the a ui pins can be wired directly to the isolation t r ans f o r me r , f or a remote m a u application, or to another d e vice ( e .g., am7992 serial inter f ace adapter) . the end-of-pa c k et sq e t est function (hea r t- beat) can be disa b led to all o w the d e vice to be em- pl o y ed in a repeater application. t wisted- p ai r t ransmit function data t r ansmission to the 10base-t medium occurs when v alid a ui signals appear on the do+/?if f erential pai r . this data stream is routed to the dif f erential d r i v er circuit r y in th e txd+/?pin s . the d r i v er circuit r y pro- vides necessa r y elect r ical d r iving capability and pre- disto r tion control f or t r ansmitting signals o v er maxim um-length twisted-pair ca b l e , as specied b y the ieee 802.3 10base-t standard . the transmit function meets the propagation del a ys and jitter specied b y the standard . du r ing t r ansmission, the xmt pin is dri v en high and can be used f or status in f o r mation. t wisted- p air receive function the recei v er complies with the recei v er speci cations of the ieee 802.3 10base-t standard, including noise imm unity and recei v ed signal rejection c r ite r ia (?ma r t squelch? . signals meeting these c r ite r ia appea r ing at the rxd+/?dif f erential input pair are routed to the di+/ output s . the recei v er function meets the propagation del a ys and jitter requirements specied b y the stan- dard . recei v er squelch l e v el drops to appr o ximately half its threshold v alue after unsquelch to all o w recep- tion of minimum amplitude signals and to offset car r ier f ade in the e v ent of worst-case signal attenuation and crosstalk noise condition s . du r ing recei v e , the rcv pin is d r i v en high and can be used f or status in f o r mation. lin k t est function the lin k t est function is implemented as specied b y the ieee 802.3 10base-t standard . du r ing pe r iods of tr ansmit pair inactivit y , lin k t est pulses will be pe r iodi- cally sent o v er the twisted-pair medium to all o w con- stant monitoring of medium inte g r it y . when the link t est function is ena b led, the absence of lin k t est pulses on the rxd+/?pair will cause th e tpex to go into a link f ail stat e . in link f ail stat e , data transmission, data reception, and the collision detection functions are disa b led, and remain disa b led until v alid data or >2 consecuti v e lin k t est pulses appear on the rxd+/ pai r . du r ing link f ail, the lnkst pin is inte r nally pulled high . when the link is identied as functional, the lnkst pin is dri v en l o w and is capa b le of directly driving a ?ink ok le d . in order to interoperate with systems that do not implement lin k t est, this function can be disa b led b y grounding the lnkst pin . when disa b led, the d r i v er and recei v er functions remain en- a b led irrespecti v e of the presence or absence of data or lin k t est pulses on the rxd+/?pai r . the transmitter contin ues to generate lin k t est pulses in the absence of t r ansmit data e v en if the lin k t est function is disa b led. p olarity detection and r e ve r sal th e tpex recei v e function includes the ability to i n v e r t the pola r ity of the signals appea r ing at the rxd pair if the pola r ity of the recei v ed signal is r e v ersed (such as in the case of a wi r ing error) . this f eature all o ws data pa c k ets recei v ed from a r e v erse-wired rxd input pair to be corrected in th e tpex p r ior to trans f er to the dte via the a ui inter f ace (di ) . the pola r ity detection func- tion is acti v ated f oll o wing reset or link f ail, and will re- v erse the recei v e pola r ity based on both the pola r ity of a n y pr e vious lin k t est pulses and the pola r ity of subse- quent pa c k ets with a v alid end transmit delimiter (etd) . when in the link f ail stat e , tpex will recogni z e link t est pulses of either positi v e or negati v e polarit y . exit from the link f ail state is caused b y the reception of v e to six consecuti v e lin k t est pulses of identical po- la r it y . on ent r y to the link p ass stat e , the pola r ity of the last v e lin k t est pulses is used to dete r mine the initial recei v e pola r ity con gu r ation and the recei v er is recon- gured to subsequently recogni z e only lin k t est pulses of the pr e viously esta b lished polarit y . this link pulse algo r ithm is empl o y ed only until etd pola r ity dete r mi- nation is mad e , as desc r ibed later in this section. p ositi v e lin k t est pulses are dened as recei v ed sig- nals with a positi v e amplitude g reater than 520 mv and a pulse width of 60 ns to 200 n s . this positi v e e xcursion m a y be f oll o wed b y a negati v e e xcursion . this denition is consistent with the e xpected recei v ed signal at a cor- rectly wired recei v er when a lin k t est pulse that ts the template of figure 14-12 in the 10base-t standard is gene r ated at a t r ansmitter and passed through 10 0 m of twisted-pair ca b l e . negati v e lin k t est pulses are dened as recei v ed sig- nals with a negati v e amplitude g reater than 520 mv and a pulse width of 60 ns to 200 n s . this negati v e e x- cursion m a y be f oll o w ed b y a positi v e e xcursion . this de nition is consistent with the e xpected recei v ed signal at a r e v erse wired recei v er when a lin k t est pulse that ts the template of figure 14-12 in the 10base-t
a m79 c98 9 standard is gene r ated at a transmitter and passed through 100 m of twisted-pair ca b l e . the pola r ity detection/correction algo r ithm will remain ? r med until t w o consecuti v e pa ck ets with v alid etd of identical pola r ity are detected . whe n ? r med , the re- cei v er is capa b le of changing the initial or pr e vious polar ity congu r ation based on the most recent etd pola r it y . on receipt of the rst pa c k et with v alid etd f oll o wing reset or link f ail , tpex will utili z e the in f erred pola r ity in f o r mation to congure its rxd input, regardless of its pr e vious stat e . on receipt of a second pa c k et with a v alid etd with correct pola r it y , the detection/correction algo r ithm wil l ?o c k in the initial pola r it y . if the second (or subsequent) pa c k et is not detected as con r ming the pr e vious pola r ity decision, the most recently de- tected etd polarity will be used as the n e w de f ault. note that pa c k ets with i n v alid etd h a v e no ef f ect on updating the pr e vious pola r ity decision . once two con- secuti v e pa c k ets with v alid etd h a v e been recei v ed, tpex will disa b le the detection/correction algorithm until either a link f ail condition occurs or prdn/rst is asse r ted. dur ing pola r ity r e v ersal, the rxpol pin is inte r nally pulled high . du r ing no r mal pola r ity condition s , the rxpol pin is dri v en l o w and is capa b le of directly d r iving a p ola r ity ok led using an integrated 16 ma d r i v e r . if desired, the pola r ity r e v ersal function can be disa b led b y grounding the rxpol pin. t wisted- p air interface status t w o outputs (xmt and rcv) indicate whethe r tpex is tr ansmitting ( a ui to twisted-pair) or receiving (twisted- pair to a ui) . both signals are asse r ted du r ing a colli- sion . in link f ail mod e , rcv is disa b led . in j a b ber detect mod e , xmt is disa b led . both signals are acti v e high. collision detect function sim ultaneous car r ier sense (presence of v alid data sig- nals) b y both the a ui do+/?pair and the rxd+/?pair constitutes a collision, there b y causing a 10 mhz signal to be asse r ted on the ci+/?output pai r . the ci+/ output meets the d r i v e requirements f or the a ui . this 10 mhz signal will remain on the ci+/?pair until one of the t w o colliding states changes from acti v e to idl e . the ci+/ output pair st a ys high f or two bit times at the end of a collision, decreasing to the idle l e v el within eighty bit times after the last l o w -to-high t r ansition . both the xmt and rcv pins are d r i v en high du r ing collision. signal quality er r or (sqe ) t est (hea r tbeat) function when th e sqe test pin is d r i v en l o w , tpex will r outinely e x ercise the collision detection circuit r y b y gene r ating an sqe message at the end of e v e r y t r ans- mission . this signal is a self-test indication to the dte that the m a u collision circuit r y is functional . an sqe message consists of a 10 mhz signal on the ci+/ pair with a du r ation of 8 bit times (800 ns) . when en- a b led, an sq e t est will occur at the end of e v e r y t r ans- mission, sta r ting eight bit times (800 ns) after the last tr ansition of the t r ansmitted signal . f or repeater appli- cation s , the sq e t est function can be disa b led b y tying the sqe test pin high or b y le a ving it disconnected . jabber function the j a b ber function inhibits the twisted-pair transmit function o f tpex if the do+/?circuit is acti v e longer than the time permitted to transmit the maximum- length 802.3/ethe r net data pa c k et (50 ms nominal). this pr e v ents a n y one node from dis r upting the net- w o r k due to a ?tu c k on or f aulty t r ansmitte r . if this maxim um transmit time is e xceeded , tpex t r ansmitter circuit r y is disa b led and a 10 mhz signal is d r i v en onto the ci+/?pai r . once the transmit data stream is re- m o v ed from the do+/?pair of input s , a n ?njab time of 250 ms to 750 ms will elapse be f or e tpex rem o v es the 10 mhz signal from the ci+/?pair and re-ena b les the tr ansmit path . p o wer d o wn in addition to on - board p o wer-on-reset circuit r y , the prdn/rst pin is used as the master reset f o r tpex. prdn/rst m ust be d r i v en l o w f or a minimum of two microseconds f or reset to occu r . the prdn/rst pin can also be used to put th e tpex into an inacti v e stat e , causing the d e vice to consume less p o we r . this f eature is useful in batte r y-p o wered or l o w-duty-cycle system s . drivin g prdn/rst l o w resets the inte r nal logic of tpex and places the d e vice into idle mod e . in this mod e , the twisted-pair d r i v er pins (txd+/?txp+/? are d r i v en l o w , the a ui pins (ci+/? di+/? are d r i v en high, the lnkst and rxpol pins are in the inacti v e stat e , and xmt and rcv are l o w . tpex will remain in idle as long as prdn/rst is asse r ted . f oll o wing the r ising edge of the signal on prdn/rst , tpex will re- main in the reset state f or 10 m s . t est modes tpex implements t w o types of loopba c k test modes suita b le f or station (dte) or repeater application s . th e t est mode is entered b y d r iving th e test pin high . the t w o types of test modes a v aila b le are: 1. station (dte) : sqe test pin l o w . data on do+/ pair is t r ansmitted onto th e txd+/?an d txp+/ pairs and data on the rxd+/?input pair is t r ansmit- ted onto the di+/?output pai r . the jabber function and collision detection functions are disa b led. 2. repeater : sqe test pin high . data on do+/ pair is looped ba c k onto the di+/?pair and data on the rxd+/?pair is ret r ansmitted on the twisted-pair d r i v ers (txd+/?an d txp+/?pairs).
10 a m7 9 c98 in both mode s , the jabber circuit r y , collision detection, and collision oscillator functions are disa b led and the a ui and rxd+/?squelch circuits are acti v e . tpex external components figure 1 sh o ws a typical twisted-pair po r t e xte r nal components schematic . the resistors used should h a v e a 1% tolerance to ensure interope r ability with 10base- t -compliant netwo r k s . filters and pulse trans- f o r mers are necessa r y d e vices that h a v e a major inu- ence on the per f o r mance and compliance of a tpex- based m a u . specicall y , the t r ansmitted w a v e f o r ms are he a vily inuenced b y lter characte r istics and the twisted-pair recei v ers empl o y s e v e r al c r ite r ia to contin- uously monitor the incoming signal s amplitude and timing cha r acte r istics to dete r mine when and if to as- se r t the inte r nal car r ier sens e . f or these reason s , it is cr ucial that the v alues and tolerances of the e xte r nal components be as speci ed . s e v e r al manu f acturers produce a module that combines the functions of the tr ansmit and recei v e lters and the pulse trans f o r mers into one pa c kag e . note: the lter/transformer module shown is available from the following manufacturers: belfuse, tdk, pulse engineering, pca, valor electronics , and nano pulse. figure 1. t ypica l t wisted- p air p o r t external components 14395 d -5 57.6 324.0 768.0 57.6 324.0 100 w am79c100 tpex txd+ txp+ txd txp rxd+ rxd xmit filter recv filter 1:1 1:1 td+ td rd+ rd t wisted- p air ca b le module

amd 1 2 AM79C98 aui connector xmt filter rcv filter rj45 connector anlg gnd anlg +5 v pulse transformer avss avdd 0.1? filter and transformer module 40.2 w 40.2 w note 1 note 2 note 3 td+ td rd+ rd 1 2 3 6 AM79C98 link ok dgtl +5 v anlg +5 v do- di+ di- ci+ ci- do+ rext test pwdn/rst sqe^test optional enable heartbeat optional 0.01? dvss dvdd xmt rcv optional dgtl gnd dgtl +5 v dgtl gnd 0.1? 24.3 k w 1% txp+ txd- txp- txd+ rxd+ rxd- xmt rcv rxpol rx pol ok 4.7? 0.1 ? anlg gnd lnkst 330 w 768.0 w 324.0 w 57.6 w 324.0 w 100 w 57.6 w 47 pf 47 pf 100 k col dgtl gnd 0.01? 74hc132 14395d-7 notes: 1. compatible filter modules, with a brief description of package type and features are included in table 1 of this section. 2. the resistor values are recommended for general purpose use, and should allow compliance to the 10base-t specification for template fit and jitter performance. however, the overall performance of the transmitter is also affected by the transmit filter configuration. 3. compatible aui transformer modules, with a brief description of package type and features are included in table 2 of this section. figure 3. typical tpex system application
amd 13 AM79C98 table 1. tpex compatible media interface modules manufacturer part # package description bel fuse a556-2006-de 16-pin 0.3 dil transmit and receive filters and transformers bel fuse 0556-2006-00 14-pin sip transmit and receive filters and transformers bel fuse 0556-2006-01 14-pin sip transmit and receive filters, transformers and common mode chokes valor electronics pt3877 16-pin 0.3 dil transmit and receive filters and transformers valor electronics pt3983 8-pin 0.3 dil transmit and receive common mode chokes valor electronics fl1012 16-pin 0.3 dil transmit and receive filters and transformers, transmit common mode choke nan o pulse np6612 16-pin 0.3 dil transmit and receive filters, transformers and common mode chokes nano pulse np6581 8-pin 0.3 dil transmit and receive common mode chokes nan o pulse np6696 24-pin 0.6 dil transmit and receive filters, transformers and common mode chokes tdk tl a 470 14-pin sip transmit and receive filters and transformers tdk him3000 24-pin 0.6 dil transmit and receive filters, transformers and common mode chokes puls e engineering pe65421 16-pin 0.3 dil transmit and receive filters and transformers puls e engineering supra 1.1 16-pin 0.5 dil transmit and receive filters and transformers, transmit common mode choke bel fuse 0556-6392-00 16-pin 0.5 dil transmit and receive filters, transformers, and common mode chokes table 2. AM79C98 tpex compatible aui transformers manufacturer part # package description bel fuse a553-0506-ab 16-pin 0.3 dil 50 m h valor electronics lt6031 16-pin 0.3 dil 50 m h tdk tl a 100-3e 16-pin 0.3 dil 100 m h puls e engineering pe64106 16-pin 0.3 dil 50 m h
amd 14 AM79C98 absolute maximum ratings storage temperature: -65 c to +150 c . . . . . . . . . . . ambient temperature under bias: 0 c to +70 c . . . . supply voltage to av ss or dv ss (av dd , dv dd ): C0.3 v to +6 v . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum rat- ings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maxi- mum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices temperature ( t a ): 0 c to +70 c . . . . . . . . . . . . . . . . supply voltages (av dd , dv dd ): +5 v 5 % . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating range unless otherwise specified parameter symbol parameter description tes t conditions min max unit digital input voltage v il input low voltage dv ss -0.5 0.8 v v ih input high voltage 2.0 0. 5 + d v dd v digital output voltage v ol output low voltag e i ol1 = 16 ma (open drain) 0.4 v i ol2 = 4.0 ma v oh output high voltage i oh = -0.4 ma 2.4 v digital input leakage current i ill input leakage current 0 < v in < dv dd + 0.5 v 1 0 m a i ild input leakage current 0 < v in < dv dd + 0.5 v 500 m a (open drain pins, output inactive) aui i iaxd input current at do+, do- -1 < vin < av dd + 0.5 v -500 500 m a v aicm do+/ - open circuit input i in = 0 v a v dd - 3.0 av dd - 1.0 v common mode voltage (bias) v aidv differential mode input av d d = 5 v -2.5 +2.5 v voltage range (do+/ - ) v asq do+/ - squelch threshold 160 -275 mv v ath do+ switching threshold (note 1) -35 +35 mv v aod differential output voltage r l = 78 w 620 1100 mv |(di+) - (di-)| or |(ci+) - (ci-)| v aodi di+/- & ci+/ - r l = 78 w -25 +25 mv differential outpu t (note 1) voltage imbalance v aod off di+/- & ci+/- r l = 78 w -40 +40 mv differential idle output voltage i aod off di+/- & ci+/- r l = 78 w -1 1 m a differential idle output current (note 1) v aocm di+/- & ci+/- common r l = 78 w 2.5 av dd v mode output voltage
amd 1 5 AM79C98 dc characteristics (continued) parameter symbol parameter description tes t conditions min max unit twisted pair interface i irxd input current at rxd+/C av ss < v in < av dd C500 500 m a r rxd rxd+/C differential input (note 1) 10 k w resistance v tivb rxd+, rxdC open circuit input i in = 0 ma av dd - 3.0 av dd - 1.5 v voltage (bias) v tidv differential mode input av dd = +5 v C3.1 3.1 v voltage range (rxd+/C) v tsq+ rxd positive sinusoid 5 mhz < f< 10 mhz 300 520 mv squelch threshold (peak) v tsqC rxd negative sinusoid 5 mhz < f< 10 mhz C520 C300 mv squelch threshold (peak) v ths+ rxd post-squelch positive sinusoid 5 mhz < f< 10 mhz 150 293 mv threshold (peak) v thsC rxd post-squelch negative sinusoid 5 mhz < f< 10 mhz C293 C150 mv threshold (peak) v rxdth rxd switching threshold (note 1) C60 60 mv v txh txd+/C and txp+/C (not e 2) dv dd - 0.6 dv dd v output high voltage dv ss = 0 v v txl txd+/C and txp+/C (not e 2) dv ss dv ss + 0.6 v output low voltage dv dd = +5 v v txi txd+/C and txp+/C C40 +40 mv differential output voltage imbalance v txoff txd+/C and txp+/ C dv dd = +5 v C40 +40 mv differential idle output voltage r tx txd+/C and txp+/C (not e 1) 40 w differential driver output impedance i irext input current at rext pin r ext = 24.3k w 1% 120 m a av dd = +5 v power supply current i dd power supply current prdn/rst = high 115 ma (transmitting 10 mhz data) (typical tp load) power supply current prdn/rst = high 90 ma (transmitting 10 mhz data) (no tp load) i ddprdn power supply current prdn/rst = low 4 m a in power down mode
amd 1 6 AM79C98 switching characteristics over commercial parameter symbol parameter description min max unit transmit timing t pwodo do pulse width |v in | > |v asq | 1 5 3 5 n s accept/reject threshold (not e 3) t pwkdo do pulse width |v in | > |v asq | 105 200 ns maintain/turn-off threshold (not e 4) t ton transmit start up delay 300 ns t tsd transmit static propagation 120 ns delay (do to txd) t dodion do to di startup delay 300 ns t dodisd do to di static propagation 100 ns delay t tetd transmit end of transmission 250 450 ns t tr transmitter rise time 10 ns (10% to 90%) t tf transmitter fall time 10 ns (90% to 10%) t tm transmitter rise and fall 4 n s time mismatch t thd do lC>h to txd+ lC>h steady state t tsd C 1.0 t tsd + 1.0 ns and txd- h->l delay (note 1) t tld do hC>l to txd+ hC>l steady state t tsd C 1.0 t tsd + 1.0 ns and txdC lC>h delay (note 1) t thdp do lC>h to txp+ hC>l steady state t tsd + 40 t tsd + 60 ns and txp- l->h delay (note 1) t tldp do hC>l to txp+ lC>h steady state t tsd + 40 t tsd + 60 ns and txpC h->l delay (note 1) t xmton xmt asserted delay 100 ns t xmtoff xmt de-asserted delay 300 ns t perlp idle signal period 8 2 4 m s t pwlp idle link test pulse width (note 1) 75 120 ns t pwplp predistortion idle link test (note 1) 40 60 ns pulse width t ja transmit jabber 20 150 ms activation time t jr transmit jabber 250 750 ms reset time t jrec transmit jabber 1.0 C m s recovery time (minimum time gap between transmitted packets to prevent jabber activation)
amd 1 7 AM79C98 switching characteristics (continued) parameter symbol parameter description min max unit receive timing t pwkrd rxd pulse width |v in | >|v ths | 136 200 ns maintain/turn-off threshold (not e 5) t ron receiver start up delay 5 mhz sinusoi d 200 400 ns (rxd to di+/C) t rvb first validly timed bi t t ro n + 100 ns on di+/C (rxd to di) t rsd receiver static propagation 70 ns delay (rxd to di) t retd di end of transmission 200 ns t rhd rxd lC>h to di+ lC>h (note 1) t rsd C 2.5 t rsd + 2.5 ns and diC hC>l delay t rld rxd hC>l to di+ hC>l (note 1) t rsd C 2.5 t rsd + 2.5 ns and di- l->h delay t rr di+, diC, ci+, ciC rise 5.0 ns time (10% to 90%) t rf di+, diC, ci+, ciC fall 5.0 ns time (10% to 90%) t rm di+/C & ci+/C rise and fal l 2.0 ns time mismatch (|t rr C t rf |) t rcvon rcv asserted delay t ron C 50 t ron + 100 ns t rcvoff rcv de-asserted delay t rsd + 250 ns collision detection and sqe test t con collision turn-on 500 ns delay (ci+/C) t coff collision turn-off 500 ns delay (ci+/C) t per collision period (ci+/C) 87 117 ns t cpw collision output pulse width 40 60 ns (ci+/-) t sqed sqe test delay time 600 1600 ns t sqel sqe test lengt h 500 1500 ns notes: 1. parameter not tested. 2. uses switching test load. 3. do pulses narrower than t pwodo (min) will be rejected; pulses wider than t pwodo (max) will turn internal do carrier sense on. 4. do pulses narrower than t pwkdo (min) will maintain internal do carrier sense on; pulses wider than t pwkdo (max) will turn internal do carrier sense off. 5. rxd pulses narrower than t pwkrd (min) will maintain internal rxd carrier sense on; pulses wider than t pwkrd (max) will turn internal rxd carrier sense off.

amd 1 9 AM79C98 switching waveforms t pwplp t pwlp t perlp txd+ txp+ txdC txpC 14395d-9 t pwplp tp idle link test pulse switching test circuits dv dd txd+ 294 w 100 pf 14395d-10 txdC dv ss 29 4 w test point includes test jig capacitance txd switching test circuit dv dd txp+ 71 5 w 100 pf 14395d-11 txpC dv ss 71 5 w test point includes test jig capacitance txp switching test circuit

amd 21 AM79C98 receive test circuit dv dd di+ diC ci+ ciC 154 w 100 pf 14395d-13 dv ss 52. 3 w test point aui di, ci switching test circuit do + / C ci + ci C t con t coff t cpw t per rxd + / C 14395d-14 collision timing 14395d-15 do + / C ci + ci C t sqed t sqel sqe test timing ( sqe^test pin connected to v ss )
trademarks copyright ?1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies.

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